Cache management through delayed writeback
US8140767B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2009 |
| Grant date | Mar 20, 2012 |
| Priority date | — |
| Expiry date | Apr 24, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/121
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The illustrative embodiments provide a method, apparatus, and computer program product for managing a number of cache lines in a cache. In one illustrative embodiment, it is determined whether activity on a memory bus in communication with the cache exceeds a threshold activity level. A least important cache line is located in the cache responsive to a determination that the threshold activity level is exceeded, wherein the least important cache line is located using a cache replacement scheme. It is determined whether the least important cache line is clean responsive to the determination that the threshold activity level is exceeded. The least important cache line is selected for replacement in the cache responsive to a determination that the least important cache line is clean. A clean cache line is located within a subset of the number of cache lines and selecting the clean cache line for replacement responsive to an absence of a determination that the least important cache line is not clean, wherein the each cache line in the subset is examined in ascending order of importance according to the cache replacement scheme.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.