Method of performing timing analysis on integrated circuit chips with consideration of process variations

US8141025B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Debjit Sinha · Wappingers Falls, US
• Eric A. Foreman · Saint Albans, US
• Peter A. Habitz · South Burlington, US
• Natesan Venkateswaran · Hopewell Junction, US
• Chandramouli Visweswariah · Croton-on-Hudson, US
• Vladimir Zolotov · Putnam Valley, US

Key dates

• Filing date: Jan 15, 2009
• Grant date: Mar 20, 2012
• Expiry date: May 29, 2030

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F30/3312
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A method for verifying whether a circuit meets timing constraints by performing an incremental static timing analysis in which slack is represented by a distribution that includes sensitivities to various process variables. The slack at an endpoint is computed by propagating the arrival times and required arrival times of paths leading up to the endpoint. The computation of arrival and required arrival times needs the computation of delays of individual gate and wire segments in each path that leads to the endpoint. The mixed mode adds a deterministic timing to the statistical timing (DSTA+SSTA).