Methods of forming inter-poly dielectric (IPD) layers in power semiconductor devices

US8143123B2 · kind B2 · utility

Assignee

• FAIRCHILD SEMICONDUCTOR CORPORATION · US

Inventors

• Thomas E. Grebs · Smethport, US
• Rodney S. Ridley · Scarborough, US
• Steven Sapp · Felton, US
• Peter H. Wilson · Boulder, US
• Babak S. Sani · Oakland, US
• Gary M. Dolny · Smethport, US
• John Mytych · Shillington, US
• Becky Losee · Cedar Hills, US
• Adam Selsley · Schenectady, US
• Christopher Boguslaw Kocon · Mountain Top, US

Key dates

• Filing date: Mar 3, 2008
• Grant date: Mar 27, 2012
• Expiry date: Mar 26, 2029

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02B70/10
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for forming power semiconductor devices having an inter-electrode dielectric (IPD) layer inside a trench includes providing a semiconductor substrate with a trench, lining the sidewalls and bottom of the trench with a first layer of dielectric material, filling the trench with a first layer of conductive material to form a first electrode, recessing the first layer of dielectric material and the first layer of conductive material to a first depth inside the trench, forming a layer of polysilicon material on a top surface of the dielectric material and conductive material inside the trench, oxidizing the layer of polysilicon material, and forming a second electrode inside the trench atop the oxidized layer and isolated from trench sidewalls by a second dielectric layer. The oxidation step can be enhanced by either chemically or physically altering the top portion polysilicon such as by implanting impurities.