Nested and isolated transistors with reduced impedance difference
US8143651B2 · kind B2 · utility
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2References
19Claims
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Key dates
| Filing date | Aug 2, 2010 |
| Grant date | Mar 27, 2012 |
| Priority date | — |
| Expiry date | Aug 2, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/601
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, Rs of transistors in iso and nested regions can be matched.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.