Methods and memory devices for repairing memory cells
US8144534B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 25, 2009 |
| Grant date | Mar 27, 2012 |
| Priority date | — |
| Expiry date | Jun 12, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/76
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and memory devices for repairing memory cells are discloses, such as a memory device that includes a main array having a plurality of sections of memory cells. One such main array includes a plurality of sets of input/output lines, each of which may be coupled to a respective plurality of memory cells in each section. One such memory device also includes a redundant section of memory cells, corresponding in number to the number of memory cells in each of the sections of the main array. An addressing circuit may contain a record of, for example, sections that have been determined to be defective. The addressing circuit may receive an address and compare the received address with the record of defective sections. In the event of a match, the addressing circuit may redirect an access to memory cells corresponding to the received address to memory cells in the redundant section.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.