Selective register reset
US8145866B2 · kind B2 · utility
2Cited by
4References
25Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 27, 2008 |
| Grant date | Mar 27, 2012 |
| Priority date | — |
| Expiry date | Jan 21, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure includes methods, devices, modules, and systems for storing selective register reset. One method embodiment includes receiving an indication of a die and a plane associated with at least one address cycle. Such a method can also include selectively resetting a particular register of a number of registers, the particular register corresponding to the plane and the die.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.