Method for assembling a wafer level test probe card
US8146245B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 2010 |
| Grant date | Apr 3, 2012 |
| Priority date | — |
| Expiry date | May 26, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49222
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for assembling a probe card for wafer level testing of a plurality of semiconductor devices simultaneously is disclosed. The probe card may include a circuit board including wafer level testing circuitry, a partially flexible silicon substrate, a plurality of test probes disposed at least partially in the substrate for engaging a plurality of corresponding electrical contacts in a wafer under test, and a compressible underfill coupling the substrate to the circuit board. The method includes aligning and assembling the foregoing components, and curing the underfill. The probe card may be used for wafer level burn-in testing. In some embodiments, the probe card may include active test control circuitry embedded in the silicon substrate for conducting wafer level high frequency testing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.