Surface patterned topography feature suitable for planarization
US8148228B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2007 |
| Grant date | Apr 3, 2012 |
| Priority date | — |
| Expiry date | Mar 10, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for manufacturing a semiconductor device that comprises implanting a first dopant type in a well region of a substrate to form implanted sub-regions that are separated by non-implanted areas of the well region. The method also comprises forming an oxide layer over the well region, such that an oxide-converted first thickness of the implanted sub-regions is greater than an oxide-converted second thickness of the non-implanted areas. The method further comprises removing the oxide layer to form a topography feature on the well region. The topography feature comprises a surface pattern of higher and lower portions. The higher portions correspond to locations of the non-implanted areas and the lower portions correspond to the implanted sub-regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.