Patent · US Active

Method and apparatus for reducing read disturb in memory

US8149624B1 · kind B1 · utility

3Cited by

2References

20Claims

0Family size

Assignee

MACRONIX INTERNATIONAL CO., LTD. · TW

Inventors

Chun-Hsiung Hung · Hsinchu, TW
Shuo-Nan Hung · Zhubei City, TW
Tseng-Yi Liu · Hsinchu, TW

Key dates

Filing date	Sep 9, 2010
Grant date	Apr 3, 2012
Priority date	—
Expiry date	Sep 30, 2030

Classification

Technology area (CPC G)Physics
CPC primaryG11C16/10
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Various aspects of a NAND memory include have multiple versions of a high threshold voltage distribution—a version with a reduced maximum, and another version. The version with a reduced maximum has a reduced word line pass voltage.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.