System and method for a semiconductor lithographic process control using statistical information in defect identification
US8150140B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2010 |
| Grant date | Apr 3, 2012 |
| Priority date | — |
| Expiry date | May 22, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T2207/30148
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method is described for evaluating a wafer fabrication process for forming patterns on a wafer based upon data. Multiple inspection regions are defined on the wafer for analysis. For each inspection region, images of patterns within the inspection region are captured, edges are detected, and lines are registered to lines of a reference pattern automatically generated from the design data. Line widths are determined from the edges. Measured line widths are analyzed to provide statistics and feedback information regarding the fabrication process. In particular embodiments defects are identified as where measured line widths lie outside boundaries determined from the statistics. In particular embodiments, lines of different drawn width and/or orientation are grouped and analyzed separately. Measured line widths may also be grouped for analysis according to geometry such as shape or proximity to other shapes in the inspection region to provide feedback for optical proximity correction rules.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.