Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency
US8151268B2 · kind B2 · utility
5Cited by
82References
16Claims
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Key dates
| Filing date | Jan 8, 2010 |
| Grant date | Apr 3, 2012 |
| Priority date | — |
| Expiry date | Oct 10, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3888
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multithreading processor for concurrently executing multiple threads is provided. The processor includes an execution pipeline and a thread scheduler that dispatches instructions of the threads to the execution pipeline. The execution pipeline execution pipeline is configured for generating a thread context (TC) flush indicator associated with a thread context when one or more instructions of the thread context would stall in the execution pipeline. One or more instructions in the pipeline of the thread context associated with the thread context flush signal can be flushed or nullified.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.