Selective spacer formation on transistors of different classes on the same device

US8154067B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Giuseppe Curello · Portland, US
• Ian R. Post · Colorado Springs, US
• Chia-Hong Jan · Portland, US
• Mark Bohr · Beaverton, US

Key dates

• Filing date: Apr 6, 2009
• Grant date: Apr 10, 2012
• Expiry date: May 5, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/60

Abstract

A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.