Near chip size semiconductor package
US8154111B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2003 |
| Grant date | Apr 10, 2012 |
| Priority date | — |
| Expiry date | Jan 15, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package that can fit semiconductor chips of various sizes without having to change the footprint of the carrier package. One aspect of the semiconductor package comprises a leadframe, a semiconductor chip attached to the leadframe, electrical connectors electrically connecting the semiconductor chip to the leadframe, and a sealing material. The leadframe has a plurality of leads, with each one of the plurality of leads having an upper side, a lower exposed side, and a laterally exposed side. The upper side of each one of the plurality of leads defines a generally co-planar surface. Further, after sealing material encapsulates the components of the semiconductor package in a spatial relationship, the lower exposed side and the lateral exposed side of the plurality of leads are exposed to the outside surface of the semiconductor package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.