High power integrated circuit device having bump pads
US8154117B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2008 |
| Grant date | Apr 10, 2012 |
| Priority date | — |
| Expiry date | Sep 17, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) includes a substrate having a semiconducting surface, a first array of devices on and in the semiconducting surface including first and second coacting current conducting nodes, a plurality of layers disposed on the substrate and including at a electrically conductive layers and dielectric layer, and a plurality of bump pads on or in the top surface of the dielectric layers. In the IC, the electrically conductive layers define electrical traces, where a first portion of the electrical traces contact a first portion of the bump pads exclusively to a portion of the first coacting current conducting nodes, where a second portion of the electrical traces contact a second portion of the bump pads exclusively to a portion of the second coacting current conducting nodes, and where the electrical traces are electrically isolated from one another by the dielectric layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.