Chip package structure
US8154125B2 · kind B2 · utility
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0References
19Claims
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Assignee
Inventor
Key dates
| Filing date | Jun 13, 2008 |
| Grant date | Apr 10, 2012 |
| Priority date | — |
| Expiry date | May 11, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A chip package structure including a carrier, a chip, and an underfill layer is disclosed. The carrier has a number of bumps disposed thereon. The chip has an active surface. The chip is flip-chip bonded and electrically connected to the carrier through the bumps such that the active surface of the chip faces the carrier. The underfill layer is disposed on the carrier between the chip and the carrier such that a gap is maintained between the underfill layer and the chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.