Fail safe adaptive voltage/frequency system
US8154335B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2009 |
| Grant date | Apr 10, 2012 |
| Priority date | — |
| Expiry date | Sep 18, 2029 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system on chip (SoC) has a digital domain. An adaptive voltage/frequency scaling circuit includes a critical path replica circuit with respect to that digital domain. The critical path replica circuit generates a margin signal, and the adaptive voltage scaling circuit responds to the margin signal by decreasing bias voltage (and/or increasing clock frequency) applied to the digital domain of the system on chip so as to recover available margin. A fail-safe timing sensor is included within the digital domain of the system on chip. The timing sensor generates a flag signal when timing criteria within the digital domain are violated. The adaptive voltage scaling circuit responds to the flag signal by increasing the bias voltage (and/or decreasing the clock frequency) applied to the digital domain of the system on chip so as to implement a recovery operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.