Integrated circuit fabrication

US8158476B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Luan C. Tran · Meridian, US
• John Lee · Boise, US
• Zengtao T. Liu · Boise, US
• Eric H. Freeman · Kuna, US
• Russell Nielsen · Boise, US

Key dates

• Filing date: Aug 4, 2010
• Grant date: Apr 17, 2012
• Expiry date: Oct 14, 2030

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/947
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.