Split-gate non-volatile memory cell having improved overlap tolerance and method therefor

US8163615B1 · kind B1 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• Ted R. White · Austin, US
• Gowrishankar L. Chindalore · Austin, US
• Brian A. Winstead · Austin, US

Key dates

• Filing date: Mar 21, 2011
• Grant date: Apr 24, 2012
• Expiry date: Mar 21, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/035

Abstract

A method for forming a split-gate non-volatile memory (NVM) cell includes forming a first gate layer over a semiconductor substrate; forming a conductive layer over the first gate layer; patterning the first gate layer and the conductive layer to form a first sidewall, wherein the first sidewall comprises a sidewall of the first gate layer and a sidewall of the conductive layer; forming a first dielectric layer over the conductive layer and the semiconductor substrate, wherein the first dielectric layer overlaps the first sidewall; forming a second gate layer over the first dielectric layer, wherein the second gate layer is formed over the conductive layer and the first gate layer and overlaps the first sidewall; and patterning the first gate layer and the second gate layer to form a first gate and a second gate, respectively, of the split-gate NVM cell, wherein the second gate overlaps the first gate and a portion of the conductive layer remains between the first gate and the second gate.