Patent · US Active

Semiconductor module arrangement

US8164176B2 · kind B2 · utility

7Cited by

8References

9Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Dirk Siepe · Dortmund, DE
Reinhold Bayerer · Warstein, DE

Key dates

Filing date	Oct 20, 2006
Grant date	Apr 24, 2012
Priority date	—
Expiry date	Nov 14, 2027

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/2076
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A semiconductor arrangement has a silicon body with a first surface and a second surface and a thick metal layer arranged on at least one surface of the silicon body. The thickness of the thick metal-layer is at least 10 micrometers (μm).

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.