Methods for generating representations of flatness defects on wafers
US8165706B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 29, 2009 |
| Grant date | Apr 24, 2012 |
| Priority date | — |
| Expiry date | Aug 2, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/67288
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Methods are disclosed for generating a representation of flatness defects on a wafer. Data is received describing the thickness of the wafer at a plurality of points on a wafer divided into a plurality of sites. A reference plane is defined for each of the plurality of sites. For each of the sites, an upper plane and a lower plane are defined relative to the reference plane. A determination is made as to which of the plurality of points on the wafer represents a flatness defect by identifying which points are not disposed between the upper plane and lower plane. A representation is then generated depicting a location of each of the flatness defects on the wafer. In some embodiments, a single representation is generated depicting the location of flatness defects on a plurality of wafers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.