Implementing instruction set architectures with non-contiguous register file specifiers
US8166281B2 · kind B2 · utility
21Cited by
14References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 4, 2009 |
| Grant date | Apr 24, 2012 |
| Priority date | — |
| Expiry date | Oct 1, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code includes processing a fixed-width instruction of a fixed-width instruction set using a non-contiguous register specifier of a non-contiguous register specification. The fixed-width instruction includes the non-contiguous register specifier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.