Self-dicing chips using through silicon vias

US8168474B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• James W. Adkisson · Jericho, US
• Panglijen Candra · South Burlington, US
• Thomas J. Dunbar · Burlington, US
• Jeffrey P. Gambino · Gresham, US
• Mark D. Jaffe · Shelburne, US
• Robert K. Leidy · Burlington, US
• Yen L. Lim · South Burlington, US

Key dates

• Filing date: Jan 10, 2011
• Grant date: May 1, 2012
• Expiry date: Jan 10, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76898
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Systems and methods simultaneously form first openings and second openings in a substrate. The first openings are formed smaller than the second openings. The method also simultaneously forms a first material in the first openings and the second openings. The first material fills the first openings, and the first material lines the second openings. The method forms a second material different than the first material in the second openings. The second material fills the second openings. The method forms a plurality of integrated circuit structures over the first material and the second material within the second openings. The method applies mechanical stress to the substrate to cause the substrate to split along the first openings.