Reduced STI topography in high-K metal gate transistors by using a mask after channel semiconductor alloy deposition

US8173501B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Stephan Kronholz · Dresden, DE
• Markus Lenski · Dresden, DE
• Richard J. Carter · Los Altos, US

Key dates

• Filing date: Dec 9, 2010
• Grant date: May 8, 2012
• Expiry date: Dec 9, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0188
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In a manufacturing strategy for providing high-k metal gate electrode structures in an early manufacturing stage, process-related non-uniformities during and after the patterning of the gate electrode structures may be reduced by providing a superior surface topography. To this end, the material loss in the isolation region may generally be reduced and a more symmetrical exposure to reactive etch atmospheres during the subsequent removal of the growth mask may be accomplished by providing an additional etch mask when removing the growth mask from the active regions of N-channel transistors, after the growth of the threshold adjusting semiconductor material on the active regions of the P-channel transistors.