Integrated circuit package system with leadframe substrate
US8174120B2 · kind B2 · utility
0Cited by
19References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 3, 2009 |
| Grant date | May 8, 2012 |
| Priority date | — |
| Expiry date | Nov 7, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit package system is provided. A dual-type leadframe having first and second rows of leads is formed. A first row of bumps is formed on an integrated circuit chip. Solder paste is placed on the first row of leads, and the first row of bumps is pressed into the solder paste on the first row of leads. The solder paste is reflow soldered to form solder and connect the integrated circuit chip to the first row of leads, and the integrated circuit chip, the first row of bumps, the solder, and the leadframe are encapsulated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.