Multiprocessor communication device and methods thereof
US8176303B2 · kind B2 · utility
0Cited by
3References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 3, 2008 |
| Grant date | May 8, 2012 |
| Priority date | — |
| Expiry date | Nov 12, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/177
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
During a boot process of a data processing device having a master bootstrap processor device and multiple slave processor devices, memory associated with the master bootstrap processor is not accessible. Accordingly, the master bootstrap processor communicates configuration information to a slave processor by writing configuration information to a register associated with the slave processor. The slave processor communicates an acknowledgment to the master bootstrap processor in response to reading the configuration information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.