Method for fabricating dual-metal gate device

US8178401B2 · kind B2 · utility

Assignee

• Freeescale Semiconductor, Inc. · US

Inventors

• David C. Gilmer · Austin, US
• Srikanth B. Samavedam · Austin, US
• Philip J. Tobin · Austin, US

Key dates

• Filing date: Sep 8, 2006
• Grant date: May 15, 2012
• Expiry date: Apr 7, 2027

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0177

Abstract

A method of fabricating a MOS transistor that comprises a dual-metal gate that is formed from heterotypical metals. A gate dielectric (34), such as HfO2, is deposited on a semiconductor substrate. A sacrificial layer (35), is next deposited over the gate dielectric. The sacrificial layer is patterned so that the gate dielectric over a first (pMOS, for example) area (32) of the substrate is exposed and gate dielectric over a second (nMOS, for example) area (33) of the substrate continues to be protected by the sacrificial layer. A first gate conductor material (51) is deposited over the remaining sacrificial area and over the exposed gate dielectric. The first gate conductor material is patterned so that first gate conductor material over the second area of the substrate is etched away. The sacrificial layer over the second area prevents damage to the underlying dielectric material as the first gate conductor material is removed.