Method of forming shallow trench isolation structures for integrated circuits
US8178417B2 · kind B2 · utility
4Cited by
7References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2008 |
| Grant date | May 15, 2012 |
| Priority date | — |
| Expiry date | Apr 10, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76229
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming shallow trench isolation (STI) structures using a multi-step etch process is disclosed. The first etch step is performed by selectively etching the substrate at a substantially higher etching rate than the mask layer to form preliminary openings having steep taper angles. The second etch step is performed by non-selectively etching the substrate to deepen the preliminary openings to form STI gaps with substantially flat bottoms.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.