Epitaxial methods for reducing surface dislocation density in semiconductor materials

US8178427B2 · kind B2 · utility

Assignees

• COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR
• S.O.I. TEC SILICON ON INSULATOR TECHNOLOGIES · FR

Inventors

• Chantal Arena · Mesa, US
• Laurent Clavelier · Grenoble, FR
• Marc Rabarot · St-Estève, FR

Key dates

• Filing date: Mar 10, 2010
• Grant date: May 15, 2012
• Expiry date: Jul 23, 2030

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/0243
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The invention provides methods and structures for reducing surface dislocations of a semiconductor layer, and can be employed during the epitaxial growth of semiconductor structures and layers comprising III-nitride materials. Embodiments involve the formation of a plurality of dislocation pit plugs to prevent propagation of dislocations from an underlying layer of material into a following semiconductor layer of material.