Test fail analysis on VLSI chips

US8180142B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Martin Eckert · Metzingen, DE
• Georg Goecke · Steinenbronn, DE
• Marta Junginger · Altdorf, DE
• Klaus Kempter · Freising, DE
• Markus Ulbricht · Tettnang, DE

Key dates

• Filing date: Dec 2, 2008
• Grant date: May 15, 2012
• Expiry date: Dec 14, 2030

Classification

• Technology area (CPC G): Physics
• CPC primary: G06T2207/30148
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Compact graphical representations of common test fail signatures and process related test fails are provided through methods of selecting, calculating and/or presenting information. The input may be a list of failing tests on a sample of devices under test from chip and/or wafer process fails. The failing tests are identified and then other tests that fail at the same time may be identified. Several graphical outputs are provided, including all possible combinations between test fails and between test fails and process fails. The dependencies are printed as sorted two dimensional bitmaps that are compact representations of the results using color codes. Subtraction of two independent bitmaps is provided, which eliminates common properties and emphasizes differences between multiple bitmaps which allows for quick identification of differences of process fails potentially different between the two different bitmaps indicating potential root causes for the selected one of the test fails.