Hybrid branch prediction device with sparse and dense prediction caches
US8181005B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2008 |
| Grant date | May 15, 2012 |
| Priority date | — |
| Expiry date | Aug 27, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3806
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for branch prediction in a microprocessor. A hybrid device stores branch prediction information in a sparse cache for no more than a common smaller number of branches within each entry of the instruction cache. For the less common case wherein an i-cache line comprises additional branches, the device stores the corresponding branch prediction information in a dense cache. Each entry of the sparse cache stores a bit vector indicating whether or not a corresponding instruction cache line includes additional branch instructions. This indication may also be used to select an entry in the dense cache for storage. A second sparse cache stores entire evicted entries from the first sparse cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.