Method for fabricating MOS transistor
US8183118B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2010 |
| Grant date | May 22, 2012 |
| Priority date | — |
| Expiry date | Nov 16, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/015
Abstract
The invention discloses a method for fabricating a MOS transistor. A substrate having thereon a gate structure is provided. A silicon nitride layer is deposited on the gate structure. A dry etching process is then performed to define a silicon nitride spacer on each sidewall of the gate structure and a recess in a source/drain region on each side of the gate structure. A transitional layer covering the gate structure and the recess is deposited. A pre-epitaxial clean process is performed to remove the transitional layer. The substrate is subjected to a pre-bake process. An epitaxial growth process is performed to grow an embedded SiGe layer in the recess. The disposable silicon nitride spacer is removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.