Memory cell with a vertically oriented transistor coupled to a digit line and method of forming the same
US8183615B2 · kind B2 · utility
0Cited by
29References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 29, 2010 |
| Grant date | May 22, 2012 |
| Priority date | — |
| Expiry date | Oct 29, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/68
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory cell, array and device include an active area formed in a substrate with a vertical transistor including a first end disposed over a first portion of the active area. The vertical transistor is formed as an epitaxial post on the substrate surface, extends from the surface of the substrate, and includes a gate formed around a perimeter of the epitaxial post. A capacitor is formed on the vertical transistor and a buried digit line vertically couples to a second portion of the active area. An electronic system and method for forming a memory cell are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.