Reversing tone of patterns on integrated circuit and nanoscale fabrication
US8183694B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2011 |
| Grant date | May 22, 2012 |
| Priority date | — |
| Expiry date | Feb 6, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7682
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process to produce an airgap on a substrate having a dielectric layer comprises defining lines by lithography where airgaps are required. The lines' dimensions are shrunk by a trimming process (isotropic etching). The tone of the patterns is reversed by applying a planarizing layer which is etched down to the top of the patterns. The photoresist is removed, leading to sub-lithographic trenches which are transferred into a cap layer and eventually into the dielectric between two metal lines. The exposed dielectric is eventually damaged, and is etched out, leading to airgaps between metal lines. The gap is sealed by the pinch-off occurring during the deposition of the subsequent dielectric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.