Fabricating product chips and die with a feature pattern that contains information relating to the product chip
US8187897B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 19, 2008 |
| Grant date | May 29, 2012 |
| Priority date | — |
| Expiry date | Feb 24, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Product chips and die, methods for fabricating product chips, and methods for tracking the identity of die after singulation from a wafer. The product chips and die include a pattern of features formed in a metallization level of a back-end-of-line (BEOL) wiring structure. The features in the pattern contain information relating to the die, such as a unique identifier that includes a wafer identification for a wafer used to fabricate the die and a product chip location for the die on the wafer. The features may be imaged with the assistance of a beam of electromagnetic radiation that penetrates into a packaged die and is altered by the presence of the features in a way that promotes imaging.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.