Patent · US Active

Apparatus and method configured to lower thermal stresses

US8188592B2 · kind B2 · utility

0Cited by

4References

24Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Peter Nelle · Munich, DE
Matthias Stecher · Munich, DE

Key dates

Filing date	Sep 8, 2011
Grant date	May 29, 2012
Priority date	—
Expiry date	Sep 8, 2031

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/351
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

An apparatus and a method configured to lower thermal stress is disclosed. One embodiment provides a semiconductor chip, a heat sink plate and a layer structure. The layer structure includes at least a diffusion solder layer and a buffer layer. The layer structure is arranged between the semiconductor chip and the heat sink plate. The buffer layer includes a material, which is soft in comparison to a material of the diffusion solder layer, and includes a layer thickness such that thermal stresses in the semiconductor chip remain below a predetermined value during temperature fluctuations within a temperature range.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.