Methods and control circuitry for programming memory cells
US8194450B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 15, 2010 |
| Grant date | Jun 5, 2012 |
| Priority date | — |
| Expiry date | Aug 12, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5621
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods of programming memory cells and control circuitry for memory arrays facilitate a reduction of program disturb. A memory cell is shifted from a first data state to a second data state if it is desired to alter a first digit of a data value of the memory cell. If it is desired to alter a second digit of the data value of the memory cell, the memory cell is shifted to a third data state if the memory cell is in the first data state and shifted to a fourth data state if the memory cell is in the second data state. The first, second, third and fourth data states correspond to respective non-overlapping ranges of threshold voltages. The threshold voltages corresponding to the fourth data state are greater than the threshold voltages corresponding to the third data state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.