Refreshing data of memory cells with electrically floating body transistors
US8194487B2 · kind B2 · utility
7Cited by
184References
74Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2008 |
| Grant date | Jun 5, 2012 |
| Priority date | — |
| Expiry date | Mar 25, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4065
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device along with circuits including the same and methods of operating the same are described. The device comprises a memory cell including one transistor. The transistor comprises a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored in memory cells of the device can be refreshed within a single clock cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.