Pillar structure for memory device and method
US8198144B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 10, 2011 |
| Grant date | Jun 12, 2012 |
| Priority date | — |
| Expiry date | Jun 10, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/884
Abstract
A method of forming a memory device. The method provides a semiconductor substrate having a surface region. A first dielectric layer is formed overlying the surface region of the semiconductor substrate. A bottom wiring structure is formed overlying the first dielectric layer and a second dielectric material is formed overlying the top wiring structure. A bottom metal barrier material is formed to provide a metal-to-metal contact with the bottom wiring structure. The method forms a pillar structure by patterning and etching a material stack including the bottom metal barrier material, a contact material, a switching material, a conductive material, and a top barrier material. The pillar structure maintains a metal-to-metal contact with the bottom wiring structure regardless of the alignment of the pillar structure with the bottom wiring structure during etching. A top wiring structure is formed overlying the pillar structure at an angle to the bottom wiring structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.