Methods of forming p-channel field effect transistors having SiGe source/drain regions
US8198194B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 23, 2010 |
| Grant date | Jun 12, 2012 |
| Priority date | — |
| Expiry date | Aug 26, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/017
Abstract
Methods of forming p-channel MOSFETs use halo-implant steps that are performed relatively early in the fabrication process. These methods include forming a gate electrode having first sidewall spacers thereon, on a semiconductor substrate, and then forming a sacrificial sidewall spacer layer on the gate electrode. A mask layer then patterned on the gate electrode. The sacrificial sidewall spacer layer is selectively etched to define sacrificial sidewall spacers on the first sidewall spacers, using the patterned mask layer as an etching mask. A PFET halo-implant of dopants is then performed into portions of the semiconductor substrate that extend adjacent the gate electrode, using the sacrificial sidewall spacers as an implant mask. Following this implant step, source and drain region trenches are etched into the semiconductor substrate, on opposite sides of the gate electrode. These source and drain region trenches are then filled by epitaxially growing SiGe source and drain regions therein.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.