Effective prefetching with multiple processors and threads

US8200905B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Gordon B. Bell · Madison, US
• Gordon Taylor Davis · Boca Raton, US
• Jeffrey H. Derby · Chapel Hill, US
• Anil Krishna · Cary, US
• Srinivasan Ramani · Cary, US
• Ken V. Vu · Cary, US
• Steve Woolet · Raleigh, US

Key dates

• Filing date: Aug 14, 2008
• Grant date: Jun 12, 2012
• Expiry date: Mar 26, 2031

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2212/6026
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A processing system includes a memory and a first core configured to process applications. The first core includes a first cache. The processing system includes a mechanism configured to capture a sequence of addresses of the application that miss the first cache in the first core and to place the sequence of addresses in a storage array; and a second core configured to process at least one software algorithm. The at least one software algorithm utilizes the sequence of addresses from the storage array to generate a sequence of prefetch addresses. The second core issues prefetch requests for the sequence of the prefetch addresses to the memory to obtain prefetched data and the prefetched data is provided to the first core if requested.