System and method for testing pattern sensitive algorithms for semiconductor design
US8201132B2 · kind B2 · utility
1Cited by
6References
8Claims
0Family size
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Key dates
| Filing date | Dec 7, 2009 |
| Grant date | Jun 12, 2012 |
| Priority date | — |
| Expiry date | Aug 11, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F1/36
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A system and method for generating test patterns for a pattern sensitive algorithm. The method comprises the steps extracting feature samples from a layout design; grouping feature samples into clusters; selecting at least one area from the layout design that covers a feature sample from each cluster; and saving each pattern layout covered by the at least one area as test patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.