Method for forming pattern of semiconductor device
US8202683B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 2009 |
| Grant date | Jun 19, 2012 |
| Priority date | — |
| Expiry date | Sep 4, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32139
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a pattern of a semiconductor device is provided. Specifically, in a method for manufacturing a NAND flash memory device using a spacer patterning process, a dummy pattern, which is not used in an actual device operation, is additionally formed in a peripheral circuit region when a photoresist pattern for forming a string pattern is formed in a cell region. As a result, the edge photoresist pattern is prevented from being bent, and a critical dimension difference between the center region and the edge region of the photoresist pattern is not generated, thereby improving a margin of DOF to obtain a reliable semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.