Stack package having reduced electrical connection length suitable for high speed operations and method of manufacturing the same
US8202762B2 · kind B2 · utility
1Cited by
3References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2011 |
| Grant date | Jun 19, 2012 |
| Priority date | — |
| Expiry date | Aug 26, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/01082
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stack package includes an upper semiconductor chip having a plurality of first bonding pads which are formed on an upper surface of the upper semiconductor chip and via-holes which are defined in the upper semiconductor chip under the respective first bonding pads; and a lower semiconductor chip attached to a lower surface of the upper semiconductor chip and having a plurality of second bonding pads which are formed on an upper surface of the lower semiconductor chip and bumps which are formed on the respective second bonding pads and are inserted into the respective via-holes to be come into the respective first bonding pads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.