Enhanced control in scan tests of integrated circuits with partitioned scan chains
US8205125B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2009 |
| Grant date | Jun 19, 2012 |
| Priority date | — |
| Expiry date | Jul 5, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318533
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A test controller implemented in an integrated circuit (IC) with partitioned scan chains provides enhanced control in performing scan tests. According to an aspect, a test controller can selectively control scan-in, scan-out and capture phases of scan tests for different scan chains of the IC to be independent. The number of pins required to interface the test controller with an external tester is less than the number of partitions that the test controller can support. According to another aspect, an IC includes a register corresponding to each partition to support transition fault (or LOS) testing. According to another aspect, an IC with partitioned scan chains includes serial to parallel and parallel to serial converters, thereby minimizing the external pins required to support scan tests.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.