Fast evaluation of average critical area for IC layouts
US8205185B2 · kind B2 · utility
1Cited by
5References
14Claims
0Family size
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Key dates
| Filing date | Aug 17, 2009 |
| Grant date | Jun 19, 2012 |
| Priority date | — |
| Expiry date | Aug 28, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for approximating the average critical area of a layout or layout region, involving summing, over all the object segments of interest, respective critical area contribution values that are dependent upon particular layout parameters of the objects, each of the contribution values being representative of a plurality of defect sizes, and being defined such that for each defect size in the plurality of defect sizes, and for a particular defect type, the contribution values collectively count all critical areas arising due to the object segments of interest only once.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.