Data processing apparatus and method for managing multiple program threads executed by processing circuitry
US8205206B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 8, 2008 |
| Grant date | Jun 19, 2012 |
| Priority date | — |
| Expiry date | Apr 20, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2209/507
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing apparatus and method are provided for managing multiple program threads executed by processing circuitry. The multiple program threads include at least one high priority program thread and at least one lower priority program thread. At least one storage unit is shared between the multiple program threads and has multiple entries for storing information for reference by the processing circuitry when executing the program threads. Thread control circuitry is used to detect a condition indicating an adverse effect caused by a lower priority program thread being executed by the processing circuitry and resulting from sharing of the at least one storage unit between the multiple program threads. On detection of such a condition, the thread control circuitry issues an alert signal, and a scheduler is then responsive to the alert signal to cause execution of the lower priority program thread causing the adverse effect to be temporarily halted, for example by causing that lower priority program thread to be de-allocated and an alternative lower priority program thread allocated in its place. This has been found to provide a particularly efficient mechanism for allowing an…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.