System and method for automatically generating test patterns for at-speed structural test of an integrated circuit device using an incremental approach to reduce test pattern count
US8209141B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2009 |
| Grant date | Jun 26, 2012 |
| Priority date | — |
| Expiry date | Oct 19, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31835
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Disclosed are embodiments of a system and method for automatically selecting and generating test patterns for an at-speed structural test of an integrated circuit device. Specifically, a test pattern generation pass is started and proceeds until the “knee” of the simulated test coverage curve is observed. Next, the test patterns are optionally reordered and some are removed. Then, another test pattern generation pass is started. The process is repeated iteratively until some predetermined final stopping criterion is met. By performing multiple test pattern generation passes and reducing the number of available test patterns that can be generated with each pass, the method exploits the initial increase in the test coverage curve inherent in each pass and limits the overall test pattern count.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.