Memory circuit system and method
US8209479B2 · kind B2 · utility
82Cited by
473References
32Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2007 |
| Grant date | Jun 26, 2012 |
| Priority date | — |
| Expiry date | Oct 19, 2028 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.