FPGA configuration bitstream protection using multiple keys
US8209545B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2010 |
| Grant date | Jun 26, 2012 |
| Priority date | — |
| Expiry date | Sep 30, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/26
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Circuits, methods, and apparatus that prevent detection and erasure of encoding or encryption keys. These encoding keys may be used to encode a configuration bitstream or other data for an FPGA or other device. An exemplary embodiment of the present invention masks a first key to form an encoding key in order to prevent detection of the first key. In a specific embodiment, the first key is encoded using a second key. The encoded key is used to encode a configuration bitstream or other data. The encoded key is stored on an FPGA or other device. When the device is to be configured, the encoded key is retrieved and used to decode the bitstream or other data. A further embodiment stores an encryption key in a one-time programmable memory (OTP) array to prevent its erasure or modification. The encoding key may be further obfuscated before storage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.