Methods of forming a hole having a vertical profile and semiconductor devices having a vertical hole
US8211804B2 · kind B2 · utility
2Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2011 |
| Grant date | Jul 3, 2012 |
| Priority date | — |
| Expiry date | Feb 11, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/513
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In a method of forming a hole, an insulation layer is formed on a substrate, and a preliminary hole exposing the substrate is formed through the insulation layer. A photosensitive layer pattern including an organic polymer is then formed on the substrate to fill the preliminary hole. An etching gas including hydrogen fluoride (HF) or fluorine (F2) is then provided onto the photosensitive layer pattern to etch the insulation layer so that width of the preliminary hole is increased.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.